The process of fabricating integrated circuits (ICs) on a semiconducting substrate, such as a silicon wafer, is highly complex and consists of a large number of steps. Each step involves many process parameters that must be tightly controlled in order to obtain consistent and accurate results. There are, however, physical factors that may cause unintentional deviations in the process at any step. Such factors may be due to variations in the substrate itself, to slight mechanical and optical inaccuracies in the processing equipment (such as defocusing due to slight misalignment), to dust and dirt and to environmental variations. The deviations in the process may be a function of time, that is—between successive wafers, or between various parts of any one wafer, or both. When any of these—process deviations becomes excessive, singly or in combination, defects may appear in some features of the IC. These defects may be manifested in one of two scales—(a) as deviations of the surface appearance, observable over a considerable area and therefore with low resolution, which are usually due to slight geometric deviations (such as in the width of conductors), and (b) as more noticeable geometric distortions in minute areas, observable at full optical resolution. We shall refer to the former (those on scale ‘a’) as “macro-defects” and to the latter (those on scale ‘b’)—as “micro-defects”, sometimes also—as just “defects”.
Since the geometry of modem ICs is defined in units on the order of 0.1-0.2 microns, the slight deviations observable in macro-defects, while occurring over large areas, must be measured with resolutions down to the order of tens of nanometers or better, which can be done only at shorter than optical wavelengths. Micro-defects, on the other hand, are generally (and by definition) of sizes such as to be detectable through optical microscopy. They may be due to microscopic disturbances in the process, such as dust particles, or they may be, as they often are, extreme manifestations of macro-defects.
Commonly, wafers in process are inspected periodically, e.g. after certain processing steps, in order to detect defects and to thus monitor the process. Currently, the entire top surface of the wafer is inspected only optically and that—with special apparatus that is designed to detect micro-defects. An example of such apparatus is the Compass inspection system, sold by Applied Materials of Santa Clara, Calif.; its essential parts, notably the optical system, illustrated by the block diagram in FIG. 1, include a light beam source, such as a laser source, optics for collimating, focusing and scanning the light beam, a wafer holder, for holding and moving the inspected wafer, at least one sensor and a processor for processing the signals from each sensor.
Detected defects are analyzed as to their number and, preferably, as to their nature. Obviously, the occurrence of a relatively large number of defects within any region, or over the entire wafer, attests to some fault or unacceptable deviation in the process and should alert the operator to try to identify the physical factor causing the deviation and to take proper remedial action—e.g. appropriately adjusting process parameters. In the case of a very large number of defects, a determination is possibly made to reject certain dies or possibly the entire wafer.
Often, detected defects are closely examined and analyzed at a separate, so-called review, phase of operation, in order to learn therefrom about the nature of the responsible process deviation or about the existence of a macro-defect and its nature, from which, again, the responsible process deviation may be deduced. Such examination is generally done at a higher resolution than that used for defects detection and may involve micro metrology techniques. It may be carried out by means of the same equipment, but often is done on a separate, very high resolution, device, such as a scanning electron microscopes (SEM)—which is extremely expensive.
This current-art procedure of learning about process deviations that cause macro-defects in the fabricated ICs by detecting micro-defects, and possibly reviewing them, has two major drawbacks: Firstly and most importantly, macro-defects must be fairly severe in order for detectable resultant micro-defects to appear; there is then a risk of deleterious further deviation in the process before it is remedied; in extreme cases, the detected defects, whether micro or macro, may already be excessive, requiring wafer rejection—which obviously represents economical loss. Secondly, the close examination and analysis of defects during the review phase involves time and costly equipment; the time delay may cause additional wafers to be adversely affected before the process deviations have been identified and corrected. It is noted that the first drawback could be averted if the entire surface could be inspected at high resolution; this procedure is, however, extremely slow and, as mentioned above, requires very expensive equipment.
There is thus a clear need for a method and apparatus that would inspect the entire surface of wafers in process, directly detecting macro-defects at levels that do not necessarily result in micro-defects and thereby providing early, or more sensitive, indications of process variations. There is, moreover, a need for such process variation monitoring apparatus to be relatively inexpensive and therefore to preferably share some parts with conventional optical defects detecting apparatus.